It is well known that high performance semiconductor integrated circuits are migrating to power supply voltages that are less than one volt. With the migration to lower power supply voltage values, any transistor threshold voltage variations among a circuit's transistors will have a significant impact on the speed and power specification of the circuit. Similarly, fluctuations in the power supply voltage will also negatively affect speed and performance. Within an SRAM (static random access memory) circuit, replica memory cells and bit lines are used to create a reference signal whose delay tracks that of the functioning memory cells and bit lines of the SRAM. The reference signal is used to generate an enable signal for a sense amplifier that controls the timing of when the sense amplifier functions to sense a bit value of a given memory cell. Whether one replica memory cell or a plurality of replica memory cells are used, such replica memory cells are typically implemented with the slowest or worst-case memory cell parameters to ensure that adequate time is provided before a sense amplifier begins sensing. While this design criteria ensures functional operation of the memory, the design criteria also ensures that the sense amplifier will continually operate at a speed of the worst-case operating parameters.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.